SMSC LAN91C111 Uživatelský manuál stáhnout pdf (Strana 1)

SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08)

Datasheet

PRODUCT FEATURES

LAN91C111

10/100 Non-PCI

Ethernet Single Chip

MAC + PHY

 Single Chip Ethernet Controller

 Dual Speed - 10/100 Mbps

 Fully Supports Full Duplex Switched Ethernet

 Supports Burst Data Transfer

 8 Kbytes Internal Memory for Receive and Transmit

FIFO Buffers

 Enhanced Power Management Features

 Optional Configuration via Serial EEPROM Interface

 Supports 8, 16 and 32 Bit CPU Accesses

 Internal 32 Bit Wide Data Path (Into Packet Buffer

Memory)

 Built-in Transparent Arbitration for Slave Sequential

Access Architecture

 Flat MMU Architecture with Symmetric Transmit and

Receive Structures and Queues

 3.3V Operation with 5V Tolerant IO Buffers (See Pin

List Description for Additional Details)

 Single 25 MHz Reference Clock for Both PHY and

MAC

 External 25Mhz-output pin for an external PHY

supporting PHYs physical media.

 Low Power CMOS Design

 Supports Multiple Embedded Processor Host

Interfaces

—ARM

—SH

— Power PC

— Coldfire

— 680X0, 683XX

— MIPS R3000

 3.3V MII (Media Independent Interface) MAC-PHY

Interface Running at Nibble Rate

 MII Management Serial Interface

 128-Pin QFP package; lead-free RoHS compliant

package also available.

 128-Pin TQFP package, 1.0 mm height; lead-free

RoHS compliant package also available.

 Commercial Temperature Range from 0°C to 70°C

(LAN91C111)

 Industrial Temperature Range from -40°C to 85°C

(LAN91C111i)

Network Interface

 Fully Integrated IEEE 802.3/802.3u-100Base-TX/

10Base-T Physical Layer

 Auto Negotiation: 10/100, Full / Half Duplex

 On Chip Wave Shaping - No External Filters

Required

 Adaptive Equalizer

 Baseline Wander Correction

 LED Outputs (User selectable – Up to 2 LED

functions at one time)

—Link

—Activity

— Full Duplex

— 10/100

— Transmit

— Receive

1 2 3 4 5 6 ... 127 128

Shrnutí obsahu

Strany 1 - MAC + PHY

SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08) DatasheetPRODUCT FEATURESLAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY  Single Chi

Strany 2

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 10 SMSC LAN91C111 REV CDATASHEETFigure 2.2 Pin Configuration - LAN91C11

Strany 3 - Table of Contents

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 100 SMSC LAN91C111 REV CDATASHEETHIGH-END ISA OR NON-BURST EISA MACHINE

Strany 4

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 101 Revision 1.91 (08-18-08)DATASHEETnIOWR nWR I/O Write strobe - asynchron

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 102 SMSC LAN91C111 REV CDATASHEETEISA 32 BIT SLAVE On EISA the LAN91C11

Strany 6 - List of Figures

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 103 Revision 1.91 (08-18-08)DATASHEETLatched W-R combined with nCMD nRD I/

Strany 7 - List of Tables

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 104 SMSC LAN91C111 REV CDATASHEETGND A1 Figure 12.3 LAN91C111 on EISA B

Strany 8 - Chapter 1 General Description

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 105 Revision 1.91 (08-18-08)DATASHEETChapter 13 Operational Description13.1

Strany 9 - Chapter 2 Pin Configurations

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 106 SMSC LAN91C111 REV CDATASHEETInput Leakage(All I and IS buffers exc

Strany 10 - 128 PIN QFP

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 107 Revision 1.91 (08-18-08)DATASHEETCAPACITANCE TA = 25°C; fc = 1MHz; VCC

Strany 11 - Chapter 3 Block Diagrams

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 108 SMSC LAN91C111 REV CDATASHEET13.3 Twisted Pair Characteristics, Tra

Strany 12 - Ethernet

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 109 Revision 1.91 (08-18-08)DATASHEET13.4 Twisted Pair Characteristics, Rec

Strany 13 - Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 11 Revision 1.91 (08-18-08)DATASHEETChapter 3 Block DiagramsThe diagram sho

Strany 14 - Chapter 4 Signal Descriptions

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 110 SMSC LAN91C111 REV CDATASHEETChapter 14 Timing DiagramsFigure 14.1

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 111 Revision 1.91 (08-18-08)DATASHEETFigure 14.2 Asynchronous Cycle - Using

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 112 SMSC LAN91C111 REV CDATASHEETFigure 14.3 Asynchronous Cycle - nADS=

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 113 Revision 1.91 (08-18-08)DATASHEETPARAMETER MIN TYP MAX UNITSt26 ARDY Lo

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 114 SMSC LAN91C111 REV CDATASHEETFigure 14.6 Burst Read Cycles - nVLBUS

Strany 19 - 6.1 Buffer Types

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 115 Revision 1.91 (08-18-08)DATASHEETFigure 14.7 Address Latching for All M

Strany 20 - 7.3 MMU Block

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 116 SMSC LAN91C111 REV CDATASHEETPARAMETER MIN TYP MAX UNITSt8 A1-A15,

Strany 21 - 7.5 MAC-PHY Interface

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 117 Revision 1.91 (08-18-08)DATASHEETPARAMETER MIN TYP MAX UNITSt8 A1-A15,

Strany 22 - 7.5.2 Management Data Timing

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 118 SMSC LAN91C111 REV CDATASHEETAC TEST TIMING CONDITIONSUnless otherw

Strany 23

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 119 Revision 1.91 (08-18-08)DATASHEETTable 14.2 Receive Timing Characterist

Strany 24

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 12 SMSC LAN91C111 REV CDATASHEETThe diagram shown in Figure 3.2 describ

Strany 25 - 7.7 Internal Physical Layer

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 120 SMSC LAN91C111 REV CDATASHEETFigure 14.13 Collision Timing, Receive

Strany 26

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 121 Revision 1.91 (08-18-08)DATASHEETFigure 14.14 Collision Timing, Transmi

Strany 27 - 7.7.3 Decoder

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 122 SMSC LAN91C111 REV CDATASHEETFigure 14.15 Jam Timingt41t40MII 100 M

Strany 28

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 123 Revision 1.91 (08-18-08)DATASHEETTable 14.4 Link Pulse Timing Character

Strany 29 - 7.7.6 Descrambler

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 124 SMSC LAN91C111 REV CDATASHEETFigure 14.16 Link Pulse TimingTPO±t42a

Strany 30

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 125 Revision 1.91 (08-18-08)DATASHEETFigure 14.17 FLP Link Pulse TimingTPO±

Strany 31

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 126 SMSC LAN91C111 REV CDATASHEETChapter 15 Package OutlinesNotes:1. Co

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 127 Revision 1.91 (08-18-08)DATASHEETNotes:1. Controlling Unit: millimeter2

Strany 33 - 7.7.8 Twisted Pair Receiver

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 128 SMSC LAN91C111 REV CDATASHEET Chapter 16 Revision HistoryTable 16.1

Strany 34

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 13 Revision 1.91 (08-18-08)DATASHEETFigure 3.3 LAN91C111 Physical Layer to

Strany 35 - 7.7.10 Start of Packet

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 14 SMSC LAN91C111 REV CDATASHEETChapter 4 Signal DescriptionsTable 4.1

Strany 36 - 7.7.11 End of Packet

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 15 Revision 1.91 (08-18-08)DATASHEETChapter 5 Description of Pin FunctionsP

Strany 37

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 16 SMSC LAN91C111 REV CDATASHEET42 44 Local Bus Clock LCLK I** Input.

Strany 38

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 17 Revision 1.91 (08-18-08)DATASHEET9 11 EEPROM Clock EESK O4 Output. 4 μs

Strany 39

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 18 SMSC LAN91C111 REV CDATASHEETNote 5.1 If the EEPROM is enabled.125 1

Strany 40 - 7.7.13 Jabber

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 19 Revision 1.91 (08-18-08)DATASHEETChapter 6 Signal Description Parameters

Strany 41 - 7.7.18 PHY Interrupt

ORDER NUMBERS:LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE)FOR 128-PIN QFP PACKAGESLAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE)FOR 128-

Strany 42 - 7.8 Reset

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 20 SMSC LAN91C111 REV CDATASHEETChapter 7 Functional Description7.1 Clo

Strany 43 - CRC (4 BYTES)

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 21 Revision 1.91 (08-18-08)DATASHEET7.4 BIU BlockThe Bus Interface Unit can

Strany 44 - 8.2 Receive Frame Status

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 22 SMSC LAN91C111 REV CDATASHEETThe MAC and external PHY communicate vi

Strany 45 - 8.3 I/O Space

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 23 Revision 1.91 (08-18-08)DATASHEETFigure 7.1 MI Serial Port Frame Timing

Strany 46 - 8.4 Bank Select Register

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 24 SMSC LAN91C111 REV CDATASHEET7.5.4 MII Packet Data Communication wit

Strany 47

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 25 Revision 1.91 (08-18-08)DATASHEETedges. RXD0 carries the least significa

Strany 48

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 26 SMSC LAN91C111 REV CDATASHEETOn the transmit side for 100Mbps TX ope

Strany 49

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 27 Revision 1.91 (08-18-08)DATASHEET10Mbps operation is similar to the 100M

Strany 50 - 8.8 Bank 0 - Counter Register

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 28 SMSC LAN91C111 REV CDATASHEET* These 5B codes are not used. For dec

Strany 51

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 29 Revision 1.91 (08-18-08)DATASHEET7.7.4 Clock and Data RecoveryClock Reco

Strany 52

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 3 Revision 1.91 (08-18-08)DATASHEETTable of ContentsChapter 1 General Descr

Strany 53

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 30 SMSC LAN91C111 REV CDATASHEETIf 25 consecutive descrambled idle patt

Strany 54

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 31 Revision 1.91 (08-18-08)DATASHEETFigure 7.4 TP Output Voltage Template -

Strany 55

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 32 SMSC LAN91C111 REV CDATASHEETTransmit Level AdjustThe transmit outpu

Strany 56

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 33 Revision 1.91 (08-18-08)DATASHEETSTP (150 Ohm) Cable ModeThe transmitter

Strany 57

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 34 SMSC LAN91C111 REV CDATASHEETTP Squelch - 100 MbpsThe squelch block

Strany 58

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 35 Revision 1.91 (08-18-08)DATASHEETEqualizer DisableThe adaptive equalizer

Strany 59

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 36 SMSC LAN91C111 REV CDATASHEETSSD) is signaled to the controller inte

Strany 60

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 37 Revision 1.91 (08-18-08)DATASHEET7.7.12 Link Integrity & AutoNegotia

Strany 61

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 38 SMSC LAN91C111 REV CDATASHEET100BASE-TX Link Integrity Algorithm -10

Strany 62 - 8.20 Bank 2 - Data Register

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 39 Revision 1.91 (08-18-08)DATASHEETThe AutoNegotiation algorithm is initia

Strany 63

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 4 SMSC LAN91C111 REV CDATASHEET8.4 Bank Select Register . . . . . . .

Strany 64

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 40 SMSC LAN91C111 REV CDATASHEETdevice halts all transmissions includin

Strany 65

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 41 Revision 1.91 (08-18-08)DATASHEETAutopolarity DisableThe autopolarity fe

Strany 66

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 42 SMSC LAN91C111 REV CDATASHEETR/LT bits are also interrupt bits if th

Strany 67

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 43 Revision 1.91 (08-18-08)DATASHEETChapter 8 MAC Data Structures and Regis

Strany 68 - 8.25 Bank 3 - RCV Register

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 44 SMSC LAN91C111 REV CDATASHEETThe receive byte count always appears a

Strany 69

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 45 Revision 1.91 (08-18-08)DATASHEETBROADCAST - Receive frame was broadcast

Strany 70 - Chapter 9 PHY MII Registers

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 46 SMSC LAN91C111 REV CDATASHEETRegardless of the functional descriptio

Strany 71

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 47 Revision 1.91 (08-18-08)DATASHEETBank 7 is a new register Bank to the SM

Strany 72

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 48 SMSC LAN91C111 REV CDATASHEETFORCOL - When set, the FORCOL bit will

Strany 73

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 49 Revision 1.91 (08-18-08)DATASHEETSQET - Signal Quality Error Test. This

Strany 74

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 5 Revision 1.91 (08-18-08)DATASHEETChapter 15 Package Outlines . . . . . .

Strany 75

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 50 SMSC LAN91C111 REV CDATASHEETABORT_ENB - Enables abort of receive wh

Strany 76

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 51 Revision 1.91 (08-18-08)DATASHEET8.9 Bank 0 - Memory Information Registe

Strany 77

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 52 SMSC LAN91C111 REV CDATASHEETRegister) and determine the duplex mode

Strany 78

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 53 Revision 1.91 (08-18-08)DATASHEETLS2A, LS1A, LS0A – LED select Signal En

Strany 79

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 54 SMSC LAN91C111 REV CDATASHEETReserved – Must be 0.8.11 Bank 1 - Conf

Strany 80

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 55 Revision 1.91 (08-18-08)DATASHEET8.12 Bank 1 - Base Address RegisterThis

Strany 81

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 56 SMSC LAN91C111 REV CDATASHEET8.14 Bank 1 - General Purpose RegisterT

Strany 82

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 57 Revision 1.91 (08-18-08)DATASHEET8.15 Bank 1 - Control RegisterRCV_BAD -

Strany 83

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 58 SMSC LAN91C111 REV CDATASHEET8.16 Bank 2 - MMU Command RegisterThis

Strany 84 - Management

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 59 Revision 1.91 (08-18-08)DATASHEETNote: When using the RESET TX FIFOS co

Strany 85

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 6 SMSC LAN91C111 REV CDATASHEETList of FiguresFigure 2.1 Pin Configurat

Strany 86

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 60 SMSC LAN91C111 REV CDATASHEETThis register is updated upon an ALLOCA

Strany 87

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 61 Revision 1.91 (08-18-08)DATASHEETTEMPTY - No transmit packets in complet

Strany 88

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 62 SMSC LAN91C111 REV CDATASHEET8.20 Bank 2 - Data RegisterDATA REGISTE

Strany 89

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 63 Revision 1.91 (08-18-08)DATASHEETThis register can be read and written a

Strany 90

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 64 SMSC LAN91C111 REV CDATASHEET LATCOL - Late Collision 16COL - 16 c

Strany 91

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 65 Revision 1.91 (08-18-08)DATASHEETFigure 8.2 Interrupt StructureTX FIFO E

Strany 92

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 66 SMSC LAN91C111 REV CDATASHEET8.22 Bank 3 - Multicast Table Registers

Strany 93

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 67 Revision 1.91 (08-18-08)DATASHEET8.23 Bank 3 - Management InterfaceMSK_C

Strany 94

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 68 SMSC LAN91C111 REV CDATASHEET8.25 Bank 3 - RCV RegisterRCV DISCRD -

Strany 95

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 69 Revision 1.91 (08-18-08)DATASHEETCYCLE NCSOUT LAN91C111 DATA BUSAEN=0A3=

Strany 96

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 7 Revision 1.91 (08-18-08)DATASHEETList of TablesTable 4.1 LAN91C111 Pin Re

Strany 97

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 70 SMSC LAN91C111 REV CDATASHEETChapter 9 PHY MII Registers Multiple Re

Strany 98

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 71 Revision 1.91 (08-18-08)DATASHEETPHY Register DescriptionD[15:0] ↓Reg

Strany 99

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 72 SMSC LAN91C111 REV CDATASHEETREGAD[4:0] Register AddressIf REGAD[4:0

Strany 100

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 73 Revision 1.91 (08-18-08)DATASHEETTable 9.2 MII Serial Port Register MAPR

Strany 101 - DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 74 SMSC LAN91C111 REV CDATASHEET9.1 Register 0. Control RegisterRST - R

Strany 102

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 75 Revision 1.91 (08-18-08)DATASHEETDPLX - Duplex modeWhen Auto Negotiation

Strany 103

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 76 SMSC LAN91C111 REV CDATASHEETREM_FLT- Remote Fault Detect‘1’ indicat

Strany 104

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 77 Revision 1.91 (08-18-08)DATASHEETNP - Next PageA ‘1’ indicates the PHY w

Strany 105

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 78 SMSC LAN91C111 REV CDATASHEET9.6 Register 16. Configuration 1- Struc

Strany 106

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 79 Revision 1.91 (08-18-08)DATASHEET9.7 Register 17. Configuration 2 - Stru

Strany 107

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 8 SMSC LAN91C111 REV CDATASHEETChapter 1 General DescriptionThe SMSC LA

Strany 108

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 80 SMSC LAN91C111 REV CDATASHEET9.8 Register 18. Status Output - Struct

Strany 109

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 81 Revision 1.91 (08-18-08)DATASHEET9.9 Register 19. Mask - Structure and

Strany 110 - Chapter 14 Timing Diagrams

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 82 SMSC LAN91C111 REV CDATASHEET9.10 Register 20. Reserved - Structure

Strany 111

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 83 Revision 1.91 (08-18-08)DATASHEETReserved:Reserved for Factory Use Reser

Strany 112

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 84 SMSC LAN91C111 REV CDATASHEETChapter 10 Software Driver and Hardware

Strany 113

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 85 Revision 1.91 (08-18-08)DATASHEET10.2 Typical Flow of Events for Transmi

Strany 114

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 86 SMSC LAN91C111 REV CDATASHEET10.3 Typical Flow of Events for Transmi

Strany 115

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 87 Revision 1.91 (08-18-08)DATASHEET10.4 Typical Flow of Event For Receive7

Strany 116

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 88 SMSC LAN91C111 REV CDATASHEETFigure 10.1 Interrupt Service RoutineIS

Strany 117

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 89 Revision 1.91 (08-18-08)DATASHEETFigure 10.2 RX INTRRX INTRWrite Ad. Ptr

Strany 118

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 9 Revision 1.91 (08-18-08)DATASHEETChapter 2 Pin ConfigurationsFigure 2.1 P

Strany 119

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 90 SMSC LAN91C111 REV CDATASHEETFigure 10.3 TX INTRTX Interrupt With AU

Strany 120

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 91 Revision 1.91 (08-18-08)DATASHEETFigure 10.4 TXEMPTY INTR (Assumes Auto

Strany 121

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 92 SMSC LAN91C111 REV CDATASHEETMEMORY PARTITIONINGUnlike other control

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 93 Revision 1.91 (08-18-08)DATASHEETmulticast packets that might not be for

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 94 SMSC LAN91C111 REV CDATASHEETFigure 10.6 Interrupt Generation for Tr

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 95 Revision 1.91 (08-18-08)DATASHEETChapter 11 Board Setup InformationThe f

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 96 SMSC LAN91C111 REV CDATASHEETSTORE and RELOAD bits of CTR will readb

Strany 126 - Chapter 15 Package Outlines

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 97 Revision 1.91 (08-18-08)DATASHEETFigure 11.1 64 X 16 Serial EEPROM MapCO

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10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 98 SMSC LAN91C111 REV CDATASHEETChapter 12 Application ConsiderationsTh

Strany 128 - Chapter 16 Revision History

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 99 Revision 1.91 (08-18-08)DATASHEETD0-D31 D0-D31 32 bit data bus. The bus

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